ASIC Design Verification Engineer
Contract San Francisco, California, United States Posted 4 years ago
About Position
ASIC Design Verification Engineer (Contract)
$50.00 / Hourly
San Francisco, California, United States
ASIC Design Verification Engineer
Contract San Francisco, California, United States Posted 4 years ago
Description
Work with researchers and architects defining verification methodologies for each of the different core IP. Define and track detailed test plans for the different modules and top levels. Implement scalable test benches including checkers, reference models, coverage groups in System Verilog. Keep track of coverage metrics and bugs encountered and fixed. Implement self-testing directed and random tests. Support post silicon bringup and debug activities. Ability to communicate clearly.
Primary Skills: 2+ years of System Verilog OVM/UVM DV experience. Knowledge of Python, Perl, shell scripting. Knowledge with assertions (SVA) or others. Knowledge of digital ASICs design flows. Bachelor
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