Design Verification Engineer
Palo Alto Networks
Contract Santa Clara, California, United States Posted 3 years ago
About Position
Design Verification Engineer (Contract)
$90.00 / Hourly
Santa Clara, California, United States
Design Verification Engineer
Contract Santa Clara, California, United States Posted 3 years ago
Description
Responsibilities will include developing the verification environment; developing test plans and coding of test cases, analyzing regression failures, and verifying the function of the ASIC at both the full chip and block level.
Skills: Minimally, we are looking for someone with
1. Min 7+ years of DV experience, with several complete and successful ASIC design/verification cycles under his/her belt
2. Strong System Verilog/UVM, C/C++, and scripting skills The following is highly desirable - Ethernet 802.
3 expertise, third-party VIP integration, Ethernet MAC/PCS bring up.
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